Generating pulse width modulated signals

ABSTRACT

A technique includes using a first signal that is produced by a counter to generate a center-aligned pulse width modulation signal having a first time profile and using the first signal to concurrently generate a pulse width modulation signal that has a second time profile that is different from the first time profile.

BACKGROUND

Pulse width modulation (PWM) may be used in a number of applications,such as motor control and switching regulator control applications, asjust a few examples. A PWM signal typically is a periodic signal, whichhas two time segments in each period: an on time interval (called the“on time”) in which the PWM signal has a first state, or level (a logicone level, for example); and an off time interval (called the “offtime”) in which the PWM signal has a second level (a logic zero level,for example). By regulating a ratio (called the “duty cycle”) of theduration of the on time to the period, the average, or DC, level of thePWM signal may be controlled for purposes of controlling an end devicethat responds to the PWM signal. For example, the duty cycle of a PWMsignal may be regulated for purposes of controlling the speed of a DCmotor.

For purposes of controlling more complex end devices, such as an ACsynchronous electrical motor, a set of PWM signals (one for each windingof the motor, for example) may be employed. Depending on theapplication, the set of PWM signals may be edge-aligned orcenter-aligned PWM signals, a distinction based on the timing of the PWMsignals relative to each other. For edge-aligned PWM signals, either onor off time boundaries of the PWM signals are aligned in time. Forexample, a set of edge-aligned PWM signals may have the beginnings ofthe respective off times aligned, although the duty cycles may varyamong the PWM signals. For center-aligned PWM signals, either the on oroff times of the PWM signals are symmetrical. For example, a set ofcenter-aligned PWM signals may have the center points of their on timesaligned, although the duty cycles may vary among the PWM signals.

SUMMARY

In an exemplary embodiment, a technique includes using a first signalthat is produced by a counter to generate a center-aligned pulse widthmodulation signal having a first time profile and using the first signalto concurrently generate a pulse width modulation signal that has asecond time profile that is different from the first time profile.

In another exemplary embodiment, an apparatus includes a counter, afirst waveform generator and a second waveform generator. The counter isadapted to generate a first signal. The first waveform generator isadapted to use the first signal to generate a center aligned pulse widthmodulation signal having a first time profile, and the second waveformgenerator is adapted to use the first signal to concurrently generate apulse width modulation signal having a second time profile that isdifferent from the first time profile.

In yet another exemplary embodiment, an apparatus includes an integratedcircuit that includes a programmable counter array and a processor thatis adapted to program the programmable counter array. The programmablecounter array includes a counter, a first waveform generator and asecond waveform generator. The counter is adapted to generate a firstsignal. The first waveform generator is adapted to use the first signalto generate a center aligned pulse width modulation signal having afirst time profile, and the second waveform generator is adapted to usethe first signal to concurrently generate a pulse width modulationsignal having a second time profile that is different from the firsttime profile.

Advantages and other desired features will become apparent from thefollowing drawings, description and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a transceiver system according to anexemplary embodiment.

FIG. 2 is a schematic diagram of a microcontroller unit of the system ofFIG. 1 according to an exemplary embodiment.

FIG. 3 is a flow diagram depicting a technique to generate acenter-aligned pulse width modulation signal according to an exemplaryembodiment.

FIGS. 4-7 depict exemplary center-aligned pulse width modulation signalsaccording to exemplary embodiments.

FIGS. 8-12 depict exemplary signals of the programmable counter array ofFIG. 2 to generate a center-aligned pulse width modulation signalaccording to exemplary embodiments.

FIG. 13 is a schematic diagram of the programmable counter array of FIG.2 according to an exemplary embodiment.

FIG. 14 is a schematic diagram of a timing controller of theprogrammable counter array of FIG. 13 according to an exemplaryembodiment.

FIG. 15 is a schematic diagram of a waveform generator for a channel ofthe programmable counter array of FIG. 13 according to an exemplaryembodiment.

FIGS. 16-20 depict exemplary signals used by the programmable counterarray of FIG. 13 to generate an edge-aligned pulse width modulationsignal according to an exemplary embodiment.

DETAILED DESCRIPTION

Referring to FIG. 1, in accordance with some embodiments that aredisclosed herein, an embedded microcontroller unit (MCU) 24 may be usedin a variety of applications, such as applications in which the MCU 24controls various aspects of a transceiver 10 (as a non-limitingexample). In this regard, the MCU 24, for this particular example, maybe part of an integrated circuit (IC), or semiconductor package 30,which also includes a radio 28. As a non-limiting example, the MCU 24and the radio 28 may collectively form a packet radio, which processesincoming and outgoing streams of packet data. To this end, thetransceiver 10 may further include a radio frequency (RF) front end 32and an antenna 36, which receives and transmits RF signals (frequencymodulated (FM) signals, for example) that are modulated with the packetdata.

As non-limiting examples, the transceiver 10 may be used in a variety ofapplications that involve communicating packet stream data overrelatively low power RF links and as such, may be used in wireless pointof sale devices, imaging devices, computer peripherals, cellulartelephone devices, etc. As a specific non-limiting example, thetransceiver 10 may be employed in a smart power meter which, through alow power RF link, communicates data indicative of power consumed by aparticular load (a residential load, for example) to a network that isconnected to a utility. In this manner, the transceiver 10 may transmitpacket data indicative of power consumed by the load to mobile meterreaders as well as to an RF-to-cellular bridge, for example. Besidestransmitting data, the transceiver 10 may also receive data from theutility or meter reader for such purposes (as non-limiting examples) asinquiring as to the status of various power consuming devices orequipment; controlling functions of the smart power meter; communicatinga message to a person associated with the monitored load, etc.

As depicted in FIG. 1, in addition to communicating with the radio 28,the MCU 24 may further communicate with other devices and in this regardmay, as examples, communicate over communication lines 54 with a currentmonitoring and/or voltage monitoring device of the smart power meter aswell as communicate with devices over a serial bus 40. In this manner,the serial bus 40 may include data lines that communicate clocked datasignals, and the data may be communicated over the serial bus 40 data innon-uniform bursts. As a non-limiting example, the serial bus may be aUniversal Serial Bus (USB) 40, in accordance with some embodiments. Asdescribed herein, in addition to containing lines to communicate data,the serial bus, such as the USB 40, may further include a power line (a5 volt power line, for example) for purposes of providing power toserial bus devices, such as the MCU 24. Various USB links 46, 48, 50 and52 may communicate via a hub 44 with USB 40 and with the transceiver 10for such purposes as communicating with a residential computer regardingpower usage of various appliances, communicating with these appliancesto determine their power usages, communicating with the appliances toregulate their power usages, etc.

Referring to FIG. 2, in accordance with some embodiments, all or part ofthe components of the MCU 24 may be part of an integrated circuit 198.For example, all or part of the components of the MCU 24 may befabricated on a single die or on multiple dies (a multi-chip module, forexample) of a semiconductor package (the semiconductor package 30, forexample, or another semiconductor package, as another example).

Among its components, the MCU 24 includes a processor core 150.Depending on the particular embodiment, the MCU 24 may not contain anyof the components depicted in FIG. 2 other than the processor core 150;may contain one or more of the components that are depicted in FIG. 2 inaddition to the processor core 150; may contain other and/or additionalcomponents than the components that are depicted in FIG. 2; and soforth. Thus, many embodiments are contemplated, which are within thescope of the appended claims. As a non-limiting example, the processorcore 150 may be a 32-bit core, such as the Advanced RISC Machine (ARM)processor core, which executes a Reduced Instruction Set Computer (RISC)instruction set. In general, the processor core 150 communicates withvarious other system components of the MCU 24, such as a memorycontroller, or manager 160, over a system bus 130. In general, thememory manager 160 controls access to various memory components of theMCU 24, such as a cache 172, a non-volatile memory 168 (a Flash memory,for example) and a volatile memory 164 (a static random access memory(SRAM), for example).

For purposes of producing clock signals for use by the components of theMCU 24, such as the processor core 150, the MCU 24 includes a clocksystem 98. In some embodiments, the clock system 98 recovers a clocksignal used in the communication of bursty data on data lines over theUSB 40 and may use this recovered clock signal as the system clocksignal. In accordance with exemplary embodiments disclosed herein, theclock system 98 provides a clock signal (called “CLKOUT” in FIG. 2)signal on a clock communication line 104, which is received by acorresponding clock input terminal of the processor core 150. Asdescribed further herein, the clock system 98 selects (based on datawritten to one or more registers 112) one of a plurality of differentfrequency clock signals to be the CLKOUT signal for purposes of clockingthe processor core 150, depending on the power consumption state of theprocessor core 150.

As non-limiting examples, the clock signals available for the clocksystem's selection includes a relatively low frequency clock signal thatmay be provided by a real time clock (RTC) oscillator of the MCU 24 (asa non-limiting example), a higher frequency clock signal that may beprovided by an internal trimmable oscillator of the MCU 24 (as anothernon limiting example), a yet higher frequency clock signal that isprovided by a boot-up oscillator of the MCU (as another non-limitingexample), and so forth. The particular clock signal that is used forpurposes of clocking the processor core 150 may be based on the currentpower consumption state of the processor core 150.

In accordance with some embodiments, the MCU 24 includes an analogsystem 96, which communicates analog signals on external analogterminals 84 of the MCU 24 and generally forms the MCU's analoginterface. As an example, the analog system 96 may include variouscomponents that receive analog signals, such as analog-to-digitalconverters (ADCs), comparators, etc.; and the analog system 96 mayinclude components (supply regulators) that furnish analog signals(power supply voltages, for example) to the terminals 84, as well asother analog components, such as current drivers.

The MCU 24 includes various digital components 90 that communicate withthe processor core 150. As non-limiting examples, the peripherals 100may include a USB interface, a universal asynchronousreceiver/transmitter (UART), a system management bus (SMB) interface, aserial peripheral (SPI) interface, and so forth. The MCU unit 24 mayinclude a crossbar switch 94, which permits the programmable assigningof the digital peripheral components 90 to digital output terminals 82of the MCU 24. In this regard, the MCU 24 may be selectively configuredto selectively assign certain output terminals 82 to the digitalperipheral components 90. The MCU 24 includes another programmabledigital component, a programmable counter array (PCA) 200, whichincludes input/output (I/O) communication lines 201 that are coupled toexternal pads and internal pads of the MCU 24. The communication lines201 may be selectively routed to output terminals of the MCU 24 via thecrossbar switch 94, in accordance with some embodiments.

In accordance with exemplary embodiments, the PCA 200 includes multiple(six, as a non-limiting example) channels, which may be used forpurposes of generating various waveforms for internal components of theMCU 24 and devices that are external to the MCU 24, as well as forpurposes of capturing/analyzing internal and external signals. Inaccordance with a non-limiting example, each channel of the PCA 200 maybe programmed, or configured (via write operations by the processor core150 over the system bus 130, for example), to operate independently ofthe other channels in one of six modes of operation: an edge-alignedpulse width modulation (PWM) mode in which the channel generates anedge-aligned PWM signal; a center-aligned PWM mode in which the channelgenerates a center-aligned PWM signal; a square wave mode in which thechannel generates a square wave; a timer/capture mode; an n-bitedge-aligned PWM mode; and a software timer mode. Moreover, depending onthe particular embodiment, the PCA 200 may provide either a singlesignal or a pair of differential signals for a given channel. Thus, manyvariations are contemplated, which are within the scope of the appendedclaims.

As further described below, although the channels of the PCA 200 may beindependently programmed to operate in one of the above-mentioned modesof operation, the channels use a common timer, or counter, of the PCA200, which establishes the waveform cycle time of the PCA 200. Morespecifically, referring to FIG. 3 in conjunction with FIG. 2, inaccordance with an exemplary embodiment, a technique 220 employed by thePCA 200 includes using (block 224) a counter signal to generate acenter-aligned PWM signal that has a first time profile and using (block228) the same counter signal to concurrently generate another PWM signal(another center-aligned PWM signal, for example), which has a secondtime profile that is different from the first time profile.

FIGS. 4-7 illustrate waveforms employed by the PCA 200 for an exampleembodiment in which three channels (depicted by exemplary channelsignals CH0, CH1 and CH2 of FIGS. 5, 6 and 7, respectively) concurrentlygenerate center-aligned PWM signals in response to a counter signalcalled “COUNTER” (see FIG. 4). For this example, the CH0, CH1 and CH2signals have on time pulses 230, 232 and 234, respectively, which areassociated with a logic one voltage level, as compared to the off timesof the signals, which are associated with a logic zero voltage level.The logic levels for the on and off time pulses may be juxtaposed, inaccordance with other exemplary embodiments. As depicted in FIGS. 5, 6and 7, the on time pulses 230, 232 and 234 are generally symmetricalabout time T₀ (for one waveform cycle) and time T₅ (for another waveformcycle).

Although, as further disclosed herein, the duty cycles, and thus, the ontimes, of the CH0, CH1 and CH2 signals are programmable and may vary,the PCA 200 generates the signals using the single COUNTER signal. Morespecifically, the COUNTER signal indicates a count value of anincrementing counter (or “up counter”) that cycles (for each waveformcycle) between first and second values. In this manner, theinitialization of the COUNTER signal to the first value (such as at timeT₀, for example) begins a given cycle for each of the channels. When thecounter reaches the second value, the current cycle terminates, and thecounter transitions back to the first value to initiate another cycle.

As a more specific example, in accordance with an exemplary embodiment,the PCA 200 uses an incrementing counter, which is initialized with azero count value to begin a given cycle and counts upwardly (asreflected by the COUNTER signal) until the count value reaches an upperlimit, which causes the end of the respective cycle and the beginning ofthe next cycle. The duration of the cycle (which is shared in common bythe channels) as well as the duty cycles of the channels are selectablevia programmable settings of the PCA 200, as further described below.

Referring back to FIG. 2, in this manner, the PCA 200 includes variousprogrammable registers to control the operations of its channels,including a programmable register 340 that may be programmed via a writeoperation over the system bus 130 to write data into the register 340,which indicates a value called “LIMIT.” The LIMIT value, in turn,specifies the duration of the waveform cycle for the PCA 200. The PCA200 further includes registers 406, which are programmable via writeoperations over the system bus 130 for purposes of storing dataindicative of values, called “CCAPV values” herein. In accordance withan exemplary embodiment, each register 406 is associated with adifferent channel of the PCA 200 and stores a CCAPV value, whichspecifies the on time for the channel. Thus, the LIMIT value is commonfor all of the channels and establishes the common waveform cycle time;and the CCAPV values establish respective on times for the channels thatgenerate PWM waveforms.

For a channel that is configured to generate a center-aligned PWMsignal, the CCAPV and LIMIT values control when the on time pulse thatbegan in the previous cycle ends and when the successive on time pulsebegins. As a more specific example, in accordance with some embodiments,the end time of a particular on time pulse, such as time T₂ for the ontime pulse 234 of FIG. 7, may be described as follows:

$\begin{matrix}{{{End}\mspace{14mu}{Time}} = {\frac{CCAPV}{2}.}} & {{Eq}.\mspace{14mu} 1}\end{matrix}$The beginning time for the successive on pulse, such as the beginningtime T₄, for the example depicted in FIG. 7, may be described asfollows:

$\begin{matrix}{{{Beginning}\mspace{14mu}{Time}} = {{Limit} - {\frac{CCAPV}{2}.}}} & {{Eq}.\mspace{14mu} 2}\end{matrix}$The duty cycle for a given center-aligned PWM cycle may be described asfollows:

$\begin{matrix}{{{Duty}\mspace{14mu}{cycle}} = {\frac{\left( {{Limit} \times 2} \right) - {CCAPV}}{{Limit} \times 2}.}} & {{Eq}.\mspace{14mu} 3}\end{matrix}$

FIGS. 8-12 depict the generation of an exemplary center-aligned PWMwaveform by the PCA 200, as illustrated by a channel signal (called“CH”) of FIG. 12. For this example, the duration of the PWM cycle (fromtime T₀ to time T₃) is established by a LIMIT value of “3.” Moreover,the duty cycle of the PWM waveform is controlled by the CCAPV value of“3” for this example. Due to the LIMIT value of 3, the COUNTER signalcycles from an initial value of zero to a final value of 3 beforere-initializing back to the zero value to begin another cycle.Therefore, as depicted in FIG. 9, beginning at time T₀, the COUNTERsignal has a value of “0,” and at time T₃ (at the end of the cycle), theCOUNTER signal transitions from a value of “3” back to a value of “0.”As further described below, the counter of the PCA 200 is clocked by aclock signal called “COUNT_EN” (see FIG. 8). In this manner, inaccordance with an exemplary embodiment, the value indicated by theCOUNTER signal changes to indicate new count values in synchronizationwith positive going, or rising, edges 256 of the COUNT_EN signal on eachcycle 250 of the COUNT_EN signal.

As can be seen from Equations 1 and 2, when the CCAPV value is an evennumber, the beginning and end times for the on time pulses are wholenumbers, which correspond to whole cycles (i.e., given rising edges 256)of the COUNT_EN signal. However, when the CCAPV value is an odd number,the beginning and end times are fractional numbers. To accommodate oddCCAPV values, the PCA 200 (in accordance with an exemplary embodiment)selectively adds a half cycle of the COUNT_EN signal to the off time ofthe center-aligned PWM waveform, depending on whether the CCAPV value isodd or even.

As a more specific example, in an exemplary embodiment, the PCA 200synchronizes, or aligns, the beginning and end times of the on pulseswith the rising edges 256 of the COUNT_EN signal when the correspondingCCAPV value is an even number. When, however, the CCAPV value is an oddnumber, the PCA 200 adds a half cycle of the COUNT_EN signal to the offtime by synchronizing, or aligning, either the beginning or end time(depending on the particular embodiment) with a negative going, orfalling, edge 258 of the COUNT_EN signal. For the specific example thatis depicted in FIGS. 8-12, due to the CCAPV value being “3,” an oddnumber, the PCA 200 synchronizes the beginning time of the on time pulsewith a falling edge 258 a of the COUNT_EN signal, as depicted at timeT₂. Therefore, although at time T₂′ the value indicated by the COUNTERsignal is “2,” which is greater than the time set forth in Eq. 2, thePCA 200 does not assert the CH signal in synchronization with thecorresponding rising edge 256 b of the COUNT_EN signal. Instead, the PCA200 adds an additional half cycle of the COUNT_EN signal to the off timeby beginning the on time pulse at time T₂, which corresponds to thesubsequent falling edge 258 a of the COUNT_EN signal. By controlling thegeneration of the PWM waveform in the above-described manner, the PCA200 is capable of generating signal changes on half cycles of thecounter frequency rather than synthesizing another clock or using ahigher frequency clock signal.

Referring to FIG. 13, in accordance with an exemplary embodiment, thePCA 200 includes a timing controller 330, which generates the COUNTERsignal that is received and used by channel controllers 300 (channelcontrollers 300 ₁, 300 ₂ . . . 300 _(N), being depicted in FIG. 13, asnon-limiting examples) to generate respective channel signals (channelsignals CH₁, CH₂ . . . CH_(N), being depicted as non-limiting examples)for their corresponding channels. In accordance with some embodiments,the timing controller 330 does not provide a counter clock signal to thechannels controllers 300. Instead, the timing controller 330 provides alogical construct for a clock signal, using the COUNTER signal andadditional signals called “HALFPHASE” and “SP,” which establish a timing(when appropriate) for adding a half cycle of the COUNT_EN signal to theoff time of a given PWM waveform. In this manner, the timing controller330 asserts the HALFPHASE signal coincident with the negative going edgeof the COUNT_EN signal (see FIGS. 8-12, for example); and the timingcontroller 330 asserts the SP signal during the second phase of theCOUNT_EN signal.

In general, each channel controller 300 includes a waveform generator310, which includes comparators 312 and 314 for purposes of generatingthe waveforms for its particular channel, as further described below. Itis noted that the CH signals may be single-ended or differentialsignals, depending on the particular embodiment.

In accordance with some embodiments, to generate a center-aligned PWMsignal, the waveform generator 310 compares the counter value indicatedby the COUNTER signal to programmable values stored in the waveformgenerator 310, which correspond to the end (Eq. 1) and beginning (Eq. 2)times. In this manner, in accordance with some embodiments, the waveformgenerator's comparator 312 compares a value derived from Eq. 1 with thevalue indicated by the COUNTER signal for purposes of determining whenthe counter value surpasses the end time. Upon such occurrence, thewaveform generator 310 begins the off interval. The comparator 314 ofthe waveform generator 310, in turn, compares the value indicated by theCOUNTER signal to the value of Eq. 2. In this manner, when the valueindicated by the COUNTER signal exceeds the begin time, the waveformgenerator 310 ends the off time and begins another on time pulse.

In accordance with some embodiments, the timing of when the on timepulse begins depends on whether the CCAPV value is odd or even andfurther depends on the states of the HALFPHASE and SP signals. As anon-limiting example, the timing controller 330 asserts (drives to alogic one level, as a non-limiting example) the SP signal to indicatewhen the counter (i.e., when the COUNT_EN clock signal) is in the secondhalf of its cycle. Conversely, in the first half of the cycle, thetiming controller 330 de-asserts (drives to a logic zero level) the SPsignal. The timing controller 330 asserts the HALFPHASE signal (drivesthe HALFPHASE signal to a logic one level, for example) to cause thewaveform generator 310 to add the half cycle. As a non-limiting example,in accordance with some embodiments, when the HALFPHASE signal isasserted and the waveform generator 310 determines that the CCAPV valueis an odd number, then the waveform generator 310 begins the next ontime pulse at the next falling edge of the COUNT_EN signal, even thoughthe comparator 314 had previously indicated (coinciding with theproceeding rising edge of the COUNT_EN signal when the counter valuechanged) that the count value exceed the value stored in the comparator314.

Among its other features, in accordance with some embodiments, the PCA200 includes a bus interface 350, which is coupled to the system bus 130(see FIG. 2, for example), for purposes of permitting the PCA 200 to beprogrammed to select the particular mode of operation of the array 200,program the LIMIT value, program the CCAPV values where appropriate forthe corresponding channels, as well as set other configurationparameters of the PCA 200. The timing controller 330 receives a CLOCK1signal, which may be a generally relatively higher frequency system busclock signal (a clock signal from the system bus 130, for example) thanthe frequency of the COUNT_EN signal. The timing controller 330effectively divides the CLOCK1 in frequency for purposes of generatingthe COUNT_EN signal, i.e., for purposes of controlling the frequency atwhich the COUNTER signal is updated.

Referring to FIG. 14, more specifically, in accordance with someembodiments, the timing controller 330 includes a counter 392 that isclocked by the COUNT_EN signal for purposes of generating the COUNTERsignal at output terminals of the counter 392. The timing controller 330further includes a frequency divider 380, which generates the COUNT_EN,COUNTER, SP and HALFPHASE signals in response to the CLOCK1 signal. Inthis regard, the CLOCK1 signal is communicated to the frequency divider380, and the frequency divider 380 receives a gated version of theCLOCK1 signal (called the “COUNTDN_EN signal” herein), as controlled bya clock controller 374. In this manner, depending on the particularprogrammable configuration of the clock controller 370, the COUNTDN_ENsignal is the CLOCK1 signal or a selected gated version of the CLOCK1signal. It is noted that, depending on the particular embodiment, theCOUNTDN_EN signal may be a frequency-divided version of the CLOCK1signal or may have the same frequency as the CLOCK1 signal.

The COUNT_EN signal, and thus, the operation of the PCA 200 in general,may be temporally suspended by halt logic 370 that that has an outputterminal 372 that is coupled to an inverting input terminal of an ANDgate 378. An output terminal 375 of the clock controller 374 is coupledto a non-inverting input terminal of the AND gate 378. As its nameimplies, the halt logic 370 permits various events (via input terminals371 of the halt logic 370) to temporarily suspend the COUNT_EN signaland thus, temporarily suspend updating of the COUNTER signal by thetiming controller 330.

In accordance with some embodiments, the frequency divider 380 includesa down counter, or decrementer 384, which is clocked by the COUNTDN_ENsignal. In general, the decrementer 384 is used by the frequency divider380 to divide by a divisor P through a process in which the decrementer384 counts down twice during a given cycle of the COUNT_EN signal. Inthis regard, the divisor P is established by a multi-bit signal called“DIVIDER[9:0],” and the decrementer 384 receives all but leastsignificant bit (LSB) of the DIVIDER[9:0] signal, i.e., receives theDIVIDER[9:1] signal. In other words, the decrementer 384 counts down avalue of P/2. For a given cycle of the COUNT_EN signal, the decrementer384 first counts down by P/2 during the first half, or phase, of thecycle; and the decrementer 384 reloads with the P/2 value again to countdown for the second phase of the cycle. A halfphase generator 388controls the loading of the decrementer 384 and generates the SP andHALFPHASE signals accordingly. Moreover, the halfphase generator 388correspondingly generates the COUNT_EN signal, i.e., generates thefalling edge of the COUNT_EN signal to coincide with the decrementer 384reaching a zero count during the first phase of the cycle and generatesthe rising edge of the COUNT_EN signal to coincide with the decrementer384 reaching a zero count during the second phase of the cycle.

Among its other features, in accordance with some embodiments, thetiming controller 330 includes an upper limit comparator 399, whichmonitors the COUNTER signal for purposes of determining when the COUNTERsignal reaches the LIMIT value, which is stored in the register 340. Inaccordance with some embodiments, upon detecting that the COUNTER signalhas reached the LIMIT value, the upper limit comparator 399 asserts(drives to a logic one value, for example) a signal called“COUNT_MATCH.” The assertion of the COUNT_MATCH signal resets to thevalue of the counter 392 to zero, in accordance with some embodiments.

As also depicted in FIG. 14, the timer controller 330 may include anupper limit holding register 396, which initially receives dataindicative of a program value for the LIMIT value and transfers thisvalue into the upper limit register 340 to update the LIMIT value duringat the appropriate time.

Note that in various embodiments, the time controller 330 and othercircuitry described herein may use other numbers of signals, othersignal levels, etc., as desired.

Referring to FIG. 15, in accordance with some embodiments, the waveformgenerator 310 includes a register 406 that receives programmed dataindicative of the CCAPV value. As also depicted in FIG. 15, the waveformgenerator 310 may further include a holding register 400 for purposes oftemporarily storing this data to permit proper timing of itsintroduction. The waveform generator 310 includes a mask generator 410,which, in general, receives programmed configuration signals to selectthe particular mode of operation for the waveform generator 310. Themask generator 410 controls steering multiplexers 414 appropriately tocontrol the values that are compared by the comparators 312 and 314; theuse of the particular comparators; the operands that are used; the modeof operation of the waveform generator 310 (i.e., whether the generator310 operates in the edge-aligned PWM mode; an n-bit edge-aligned PWMmode; a center-aligned PWM mode; a square wave mode (a mode in which thechannel signal swings negative or a mode in which the channel signaldoes not swing negative, depending on the particular implementation); atimer/capture mode or a software timer mode); and so forth. Other anddifferent modes of operation are contemplated and are within the scopeof the appended claims.

In accordance with some embodiments, a single comparator 312 may be usedby the waveform generator 310 for five of the six modes, with thecenter-aligned PWM mode of operation employing the use of bothcomparators 312 and 314. A state generator 422 of the waveform generator310 uses the comparators 418 for purposes of determining when to assertand de-assert the channel CH signal. Thus, as set forth above, duringthe center-aligned PWM mode of operation, the state generator 422 usesthe comparator 312 for purposes of determining the ending time for theon pulse and controlling the CH signal accordingly; and the stategenerator 422 uses the comparator 314 for purposes of determining thebeginning time for the on pulse and controlling the state of the CHsignal accordingly.

Among its other features, in accordance with some embodiments, thewaveform generator 310 includes a phase generator 426, which generatesgenerally complimentary signals, which may be used for motor controlapplications and which includes appropriate dead times that may be setby corresponding programmable settings. The waveform generator 310 mayfurther include capture logic 404, which is configured via configurationlines 430 and receives an external input signal (called “CEX_IN signal”in FIG. 15), which is monitored by the capture logic 404 in the capturemode of operation for purposes of detecting states of the CEX_IN signal.

In accordance with some embodiments, the PCA 200 may also use theabove-described half cycle control for purposes of generating PWMwaveforms, other than center-aligned PWM waveforms. In this regard, as anon-limiting example, in accordance with some embodiments, during anedge-aligned PWM mode, the waveform generator 310 may use a singlecomparator 312 for purposes of comparing the count value to anappropriate value derived from the CCAPV value for purposes ofdetermining when to begin the on time of a particular edge aligned PWMwaveform. As a more specific example, FIG. 16 (depicting the COUNT_ENsignal), FIG. 17 (depicting the COUNTER signal), FIG. 18 (depicting theLIMIT value), FIG. 19 (depicting the CCAPV value) and FIG. 20 (depictingthe CH signal) depict an example for which the LIMIT value is 3 and theCCAPV value is “3” for an edge-aligned PWM waveform. Due to thealignment of the off time of the PWM waveform with leading edge of thecycle, the PWM waveform begins in synchronization with a correspondingrising edge 256 c of the COUNT_EN signal and ends with another risingedge 256 b of the COUNT_EN signal, as set by the duration established bythe LIMIT value. The waveform generator, in turn, determines theappropriate time to begin the on time pulse for the PWM waveform, whichis time T₁. In general, the waveform generator 310 compares the countervalue to the (CCAPV/2) value to determine when to begin the on timepulse. However, as depicted in this example, when the CCAPV value is odd(such as 3, here), the waveform generator 310 delays the beginning ofthe on time pulse by a half cycle, i.e., begins the on time pulse attime T₁ in synchronization, or alignment with, the falling edge 258 c ofthe COUNT_EN signal.

While a limited number of embodiments have been disclosed herein, thoseskilled in the art, having the benefit of this disclosure, willappreciate numerous modifications and variations therefrom. It isintended that the appended claims cover all such modifications andvariations.

What is claimed is:
 1. A method comprising: using a first signalproduced by a counter to generate a center-aligned pulse widthmodulation signal having a first time profile; using the first signal toconcurrently generate a pulse width modulation signal having a secondtime profile different from the first time profile; and using the firstsignal to generate at least one additional signal having a third timeprofile different from the first and second time profiles.
 2. The methodof claim 1, wherein using the first signal to generate the firstcenter-aligned pulse width modulation signal comprises using the firstsignal to generate a center-aligned pulse width modulation signal havinga first duty cycle; and using the first signal to generate a secondpulse width modulation signal comprises using the first signal togenerate a second pulse width modulation signal that is center-alignedrelative to the first center-aligned pulse width modulation signal andhas a second duty cycle different from the first duty cycle.
 3. Themethod of claim 1, wherein using the first signal to generate the atleast one additional signal comprises using the first signal to generatean edge-aligned pulse width modulation signal.
 4. The method of claim 1,further comprising: frequency dividing a first clock signal to generatea second clock signal; clocking a counter with the second clock signalto generate the first signal; and generating a phase signal identifyinga phase of the second clock signal, wherein using the first signal togenerate the center-aligned pulse width modulation signal comprisesgenerating the center-aligned pulse width modulation signal based atleast in part on the phase signal and the first signal.
 5. The method ofclaim 4, wherein using the first signal to generate the center-alignedpulse width modulation signal further comprises selectively adding afractional period of the second clock signal to a pulse width of thecenter-aligned pulse width modulation signal based at least in part onthe phase signal and a determination of whether a programmable pulsewidth value indicative of a corresponding number of cycles of the firstsignal is even or odd.
 6. The method of claim 1, wherein using the firstsignal to generate the first center-aligned pulse width modulationsignal comprises: comparing a value indicated by the first signal to avalue indicative of a first time boundary of a pulse width of thecenter-aligned pulse width modulation signal; comparing the valueindicated by the first signal to a value indicative of a second timeboundary of the pulse width of the center-aligned pulse width modulationsignal; and generating the center-aligned pulse width modulation signalbased at least in part on the comparisons to the first and second timeboundaries.
 7. An apparatus comprising: a counter to generate a firstsignal; a first waveform generator to use the first signal to generate acenter-aligned pulse width modulation signal having a first duty cycle;and a second waveform generator to use the first signal to concurrentlygenerate another pulse width modulation signal having a second dutycycle different from the first duty cycle.
 8. The apparatus of claim 7,wherein the another pulse width modulation signal comprises anothercenter-aligned pulse width modulation signal.
 9. The apparatus of claim7, further comprising: a frequency divider to divide a frequency of afirst clock signal to generate a second clock signal to clock thecounter; and a phase identification circuit to generate a phase signalidentifying a phase of the second clock signal, wherein the firstwaveform generator is adapted to generate the center-aligned pulse widthmodulation signal based at least in part on the phase signal and thefirst signal.
 10. The apparatus of claim 9, wherein the first waveformgenerator is further adapted to selectively add a fractional period ofthe second clock signal to a pulse width of the center-aligned pulsewidth modulation signal based at least in part on the phase signal andwhether a programmable pulse width value indicative of a number ofcycles of the first signal is even or odd.
 11. The apparatus of claim 7,wherein the first waveform generator comprises: a first comparator tocompare a value indicative of the first signal to a value indicative ofa first time boundary of a pulse width of the center-aligned pulse widthmodulation signal; and a second comparator to compare the valueindicative of the first signal to a value indicative of a second timeboundary of the pulse width of the center-aligned pulse width modulationsignal, wherein the second waveform generator is further adapted togenerate the center-aligned pulse width modulation signal based at leastin part on signals provided by the first and second comparators.
 12. Anapparatus comprising: an integrated circuit comprising a programmablecounter array and a processor to program the programmable counter array,wherein the programmable counter array is adapted to generate a firstsignal indicative of a count, the programmable counter array comprising:a first waveform generator to use the first signal to generate acenter-aligned pulse width modulation signal having a first duty cycle;and a second waveform generator to use the first signal to concurrentlygenerate another pulse width modulation signal having a second dutycycle different from the first duty cycle.
 13. The apparatus of claim12, wherein the another pulse width modulation signal comprises anothercenter-aligned pulse width modulation signal.
 14. The apparatus of claim12, further comprising at least one additional waveform generator togenerate at least one additional signal having a third time profiledifferent from the first and second time profiles.
 15. The apparatus ofclaim 14, wherein the at least one additional waveform generatorcomprises a waveform generator adapted to generate an edge-aligned pulsewidth modulation signal.
 16. The apparatus of claim 12, wherein theprogrammable counter array further comprises: a phase identificationcircuit to generate a phase signal identifying a phase of a clock signalof the programmable counter array, wherein the first waveform generatoris adapted to generate the center-aligned pulse width modulation signalbased at least in part on the phase signal and the first signal.
 17. Theapparatus of claim 16, wherein the first waveform generator is furtheradapted to selectively add a fractional period of the second clocksignal to a pulse width of the center-aligned pulse width modulationsignal based at least in part on the phase signal and whether aprogrammable pulse width value indicative of a number of cycles of theclock signal is even or odd.
 18. The apparatus of claim 12, wherein thefirst waveform generator comprises: a first comparator to compare avalue indicative of the first signal to a value indicative of a firsttime boundary of a pulse width of the center-aligned pulse widthmodulation signal; and a second comparator to compare a value indicativeof the first signal to a value indicative of a second time boundary ofthe pulse width of the center-aligned pulse width modulation signal,wherein the first waveform generator is further adapted to generate thecenter-aligned pulse width modulation signal based at least in part onsignals provided by the first and second comparators.
 19. The apparatusof claim 12, wherein the programmable counter array comprises at leastone register to be programmed with data to define the first and secondtime profiles.